74LVT373SJ集成電路（IC）的鎖存器規(guī)格書(shū)PDF中文資料

74LVT373SJ屬于集成電路（IC）的鎖存器。由安森美半導(dǎo)體公司制造生產(chǎn)的74LVT373SJ鎖存器鎖存器是類(lèi)似于觸發(fā)器的基本數(shù)字存儲(chǔ)設(shè)備，但是不同之處在于，在鎖存使能（或類(lèi)似命名）信號(hào)處于有效邏輯狀態(tài)的任何時(shí)間，保持的邏輯狀態(tài)都可以改變?！巴该鳌辨i存器還允許設(shè)備輸出在鎖存使能信號(hào)有效時(shí)反映輸入的當(dāng)前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時(shí)改變。

General Description

The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in a high impedance state.

Features

■ Input and output interface capability to systems at 5V VCC

■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH373), also available without bushold feature (74LVT373)

■ Live insertion/extraction permitted

■ Power Up/Down high impedance provides glitch-free bus loading

■ Outputs source/sink –32 mA/+64 mA

■ Functionally compatible with the 74 series 373

■ ESD performance:

– Human-body model > 2000V

– Machine model > 200V

– Charged-device model > 1000V