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74LVQ20M中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書

74LVQ20M
廠商型號(hào)

74LVQ20M

功能描述

DUAL 4-INPUT NAND GATE

文件大小

153.41 Kbytes

頁面數(shù)量

8

生產(chǎn)廠商 STMicroelectronics
企業(yè)簡(jiǎn)稱

STMICROELECTRONICS意法半導(dǎo)體

中文名稱

意法半導(dǎo)體(ST)集團(tuán)官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二原廠數(shù)據(jù)手冊(cè)到原廠下載

更新時(shí)間

2024-11-16 20:00:00

74LVQ20M規(guī)格書詳情

DESCRIPTION

The 74LVQ20 is a low voltage CMOS DUAL 4-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.

The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 5.3 ns (TYP.) at VCC = 3.3 V

■ COMPATIBLE WITH TTL OUTPUTS

■ LOW POWER DISSIPATION: ICC = 2μA(MAX.) at TA=25°C

■ LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V

■ 75? TRANSMISSION LINE DRIVING CAPABILITY

■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V

■ PCI BUS LEVELS GUARANTEED AT 24 mA

■ BALANCED PROPAGATION DELAYS: tPLH ? tPHL

■ OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 20

■ IMPROVED LATCH-UP IMMUNITY

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫存 備注 價(jià)格
ST/意法
23+
NA/
8380
原裝現(xiàn)貨,當(dāng)天可交貨,原型號(hào)開票
詢價(jià)
FSC
2019+
SOP7.2
9850
公司原裝現(xiàn)貨/長(zhǎng)期供應(yīng)
詢價(jià)
FAIRCHILD/仙童
24+
SOP7.2MM
47
大批量供應(yīng)優(yōu)勢(shì)庫存熱賣
詢價(jià)
Fairchild/ON
22+
20QSOP
9000
原廠渠道,現(xiàn)貨配單
詢價(jià)
FAI
2018+
SOP20
6528
只做原裝正品假一賠十!只要網(wǎng)上有上百分百有庫存放心
詢價(jià)
FAIRCHILD
17+
SOP
6200
100%原裝正品現(xiàn)貨
詢價(jià)
24+
5000
公司存貨
詢價(jià)
ST/意法
23+
SOP-20L
3000
一級(jí)代理原廠VIP渠道,專注軍工、汽車、醫(yī)療、工業(yè)、
詢價(jià)
FAIRCHILD
22+23+
SOP
20508
絕對(duì)原裝正品全新進(jìn)口深圳現(xiàn)貨
詢價(jià)
FAIRCHI
2020+
SOP
80000
只做自己庫存,全新原裝進(jìn)口正品假一賠百,可開13%增
詢價(jià)