General description

The 74LVC16244A; 74LVCH16244A are 16-bit non-inverting buffer/line drivers with 3-state bus compatible outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. It features four output enable inputs, (1OE to 4OE) each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state.

Features and benefits

■ 5 V tolerant inputs/outputs for interfacing with 5 V logic

■ Wide supply voltage range from 1.2 V to 3.6 V

■ CMOS low power consumption

■ Multibyte flow-through standard pin-out architecture

■ Low inductance multiple power and ground pins for minimum noise and ground bounce

■ Direct interface with TTL levels

■ High-impedance when VCC = 0 V

■ All data inputs have bus hold. (74LVCH16244A only)

■ Complies with JEDEC standard:

◆ JESD8-7A (1.65 V to 1.95 V)

◆ JESD8-5A (2.3 V to 2.7 V)

◆ JESD8-C/JESD36 (2.7 V to 3.6 V)

■ ESD protection:

◆ HBM JESD22-A114F exceeds 2000 V

◆ MM JESD22-A115-B exceeds 200 V

◆ CDM JESD22-C101E exceeds 1000 V

■ Specified from -40 °C to +85 °C and -40 °C to +125 °C

74LVC16244ABQ屬于集成電路（IC） > 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器。恩智浦半導(dǎo)體公司制造生產(chǎn)的74LVC16244ABQ緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動(dòng)器、接收器和收發(fā)器允許隔離對某個(gè)電路的邏輯信號(hào)的訪問，以用于另一電路。緩沖器將其輸入信號(hào)（不變或反相）傳遞到其輸出，并可能用于清除弱信號(hào)或驅(qū)動(dòng)負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進(jìn)行隔離通信。