74LV540APW集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器規(guī)格書PDF中文資料

1. General description

The 74LV540A is an 8-bit inverting buffer/line driver with 3-state outputs. The device

features two output enables (OE1 and OE2). A HIGH on OEn causes the associated

outputs to assume a high-impedance OFF-state.

Inputs are overvoltage tolerant. This feature allows the use of these devices as translators

in mixed voltage environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall

times.

This device is fully specified for partial power down applications using IOFF. The IOFF

circuitry disables the output, preventing the potentially damaging backflow current through

the device when it is powered down.

2. Features and benefits

? Wide supply voltage range from 2.0 V to 5.5 V

? Maximum tpd of 6 ns at 5 V

? Typical VOL(p) < 0.8 V at VCC = 3.3 V, Tamb = 25 ?C

? Typical VOH(v) > 2.3 V at VCC = 3.3 V, Tamb = 25 ?C

? Supports mixed-mode voltage operation on all ports

? IOFF circuitry provides partial Power-down mode operation

? Latch-up performance exceeds 250 mA per JESD 78 Class II

? ESD protection:

? HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 3 kV

? MM JESD22-A115-A exceeds 150 V

? CDM JESD22-C101E exceeds 2 kV

? Specified from ?40 ?C to +85 ?C and from ?40 ?C to +125 ?C