74LS259中文資料仙童半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

General Description

These 8-bit addressable latches are designed for general purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches, and being a 1-of-8 decoder or demultiplexer with active-high outputs.

Four distinct modes of operation are selectable by controlling the clear and enable inputs as enumerated in the function table. In the addressable-latch mode, data at the data in terminal is written into the addressed latch. The addressed latch will follow the data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held HIGH (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output will follow the level of the D input with all other outputs LOW. In the clear mode, all outputs are LOW and unaffected by the address and data inputs.

Features

■ 8-Bit parallel-out storage register performs serial-to-parallel

conversion with storage

■ Asynchronous parallel clear

■ Active high decoder

■ Enable/disable input simplifies expansion

■ Direct replacement for Fairchild DM9334

■ Expandable for N-bit applications

■ Four distinct functional modes

■ Typical propagation delay times:

Enable-to-output 18 ns

Data-to-output 16 ns

Address-to-output 21 ns

Clear-to-output 17 ns

■ Fan-out

IOL (sink current) 8 mA

IOH (source current) ?0.4 mA

■ Typical ICC 22 mA