Features

■ 5 V tolerant inputs and outputs

■ High speed

– tPD = 5.2 ns (max.) at VCC = 3 V

■ Power-down protection on inputs and outputs

■ Symmetrical output impedance

– |IOH| = IOL = 24 mA (min.) at VCC = 3 V

■ PCI bus levels guaranteed at 24 mA

■ Balanced propagation delay

– tPLH ? tPHL

■ Operating voltage range

– VCC (opr.) = 2.0 V to 3.6 V

■ Pin and function compatible with 74 series 125

■ Latch-up performance exceeds 500 mA

(JESD 17)

■ ESD performance

– HBM: 2000 V (MIL STD 883 method 3015)

– MM: 200 V

– CDM: 1000 V

Applications

■ Automotive

■ Industrial

■ Computer

■ Consumer

Description

The 74LCX125 device is a low-voltage CMOS

quad bus buffer manufactured with sub-micron

silicon gate and double-layer metal wiring C2MOS

technology. It is ideal for low-power and highspeed

3.3 V applications and can be interfaced to

a 5 V signal environment for both inputs and

outputs.

The device requires the 3-state control input G to

be set high to place the output in the high

impedance state.

It has the same speed performance at 3.3 V as

the 5 V AC/ACT family, combined with lower

power consumption.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2 kV ESD immunity and transient excess

voltage.

74LCX125YMTR屬于集成電路（IC） > 緩沖器，驅(qū)動器，接收器，收發(fā)器。意法半導(dǎo)體（ST）集團制造生產(chǎn)的74LCX125YMTR緩沖器，驅(qū)動器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動器、接收器和收發(fā)器允許隔離對某個電路的邏輯信號的訪問，以用于另一電路。緩沖器將其輸入信號（不變或反相）傳遞到其輸出，并可能用于清除弱信號或驅(qū)動負載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進行隔離通信。