74HCT165PW-Q100集成電路（IC）的移位寄存器規(guī)格書PDF中文資料

1. General description

The 74HC165-Q100; 74HCT165-Q100 are 8-bit serial or parallel-in/serial-out shift registers.

The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two

complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from

D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH data enters the register

serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH

transitions of the CP input. A HIGH on CE will disable the CP input. Inputs are overvoltage tolerant

to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

? Automotive product qualification in accordance with AEC-Q100 (Grade 1)

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C

? Asynchronous 8-bit parallel load

? Synchronous serial input

? Complies with JEDEC standard no. 7A

? Input levels:

? For 74HC165-Q100: CMOS level

? For 74HCT165-Q100: TTL level

? ESD protection:

? MIL-STD-883, method 3015 exceeds 2000 V

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

? DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of

solder joints

3. Applications

? Parallel-to-serial data conversion