74HC4052中文資料恩智浦數(shù)據(jù)手冊PDF規(guī)格書

General description

The 74HC4052; 74HCT4052 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4052B. The device is specified in compliance with JEDEC standard no. 7A.

Features and benefits

■ Wide analog input voltage range from ?5 V to +5 V

■ Low ON resistance:

◆ 80 Ω (typical) at VCC - VEE = 4.5 V

◆ 70 Ω (typical) at VCC - VEE = 6.0 V

◆ 60 Ω (typical) at VCC - VEE = 9.0 V

■ Logic level translation: to enable 5 V logic to communicate with ?5 V analog signals

■ Typical ‘break before make’ built-in

■ Complies with JEDEC standard no. 7A

■ ESD protection:

◆ HBM JESD22-A114F exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

◆ CDM JESD22-C101E exceeds 1000 V

■ Specified from -40 °C to +85 °C and -40 °C to +125 °C

Applications

■ Analog multiplexing and demultiplexing

■ Digital multiplexing and demultiplexing

■ Signal gating