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74HC137DB集成電路（IC）的信號開關多路復用器解碼器規(guī)格書PDF中文資料

廠商型號	74HC137DB
參數(shù)屬性	74HC137DB 封裝/外殼為16-SSOP（0.209"，5.30mm 寬）；包裝為托盤；類別為集成電路（IC）的信號開關多路復用器解碼器；產(chǎn)品描述：IC DECODER/DEMUX 1X3:8 16SSOP
功能描述	3-to-8 line decoder, demultiplexer with address latches; inverting
封裝外殼	16-SSOP（0.209"，5.30mm 寬）
文件大小	273.83 Kbytes
頁面數(shù)量	16 頁
生產(chǎn)廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-2-26 23:00:00
人工找貨	74HC137DB價格和庫存，歡迎聯(lián)系客服免費人工找貨

1. General description

The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually

exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1,

E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to HIGH

transition on LE stores the data that was present before the transition in the latches. Further

address changes are ignored as long as LE remains HIGH.

The output enable inputs control the state of the outputs independently of the address inputs or

latch operation. All outputs will be HIGH unless E1 is LOW and E2 is HIGH.

Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to

voltages in excess of VCC.

2. Features and benefits

? Combines 3-to-8 decoder with 3-bit latch

? Multiple input enable for easy expansion or independent controls

? Active LOW mutually exclusive outputs

? Wide supply voltage range from 2.0 to 6.0 V

? CMOS low power dissipation

? High noise immunity

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Complies with JEDEC standards

? JESD8C (2.7 V to 3.6 V)

? JESD7A (2.0 V to 6.0 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Specified from -40 °C to +80 °C and from -40 °C to +125 °C.