74F219A中文資料飛利浦數據手冊PDF規(guī)格書

DESCRIPTION

The 74F219A is a high speed, 64–bit RAM organized as a 16–word by 4–bit array. Address inputs are buffered to minimize loading and are fully decoded on chip. The outputs are in high impedance state whenever the chip enable (CE) is high. The outputs are active only in the READ mode (WE = high) and the output data is the complement of the stored data.

FEATURES

? High speed performance

? Replaces 74F219

? Address access time: 8ns max vs 28ns for 74F219

? Power dissipation: 4.3mW/bit typ

? Schottky clamp TTL

? One chip enable

? Non–Inverting outputs (for inverting outputs see 74F189A)

? 3–state outputs

? 74F219A in 150 mil wide SO is preferred options for new designs

? C3F219A in 300 mil wide SOL replaces 74F219 in existing designs

APPLICATIONS

? Scratch pad memory

? Buffer memory

? Push down stacks

? Control store