74AVC16374DGG集成電路（IC）的觸發(fā)器規(guī)格書(shū)PDF中文資料

1. General description

The 74AVC16374 is a 16-bit edge triggered flip-flop featuring separate D-type inputs for

each flip-flop and 3-state outputs for bus-oriented applications. The 74AVC16374 consist

of 2 sections of 8 edge-triggered flip-flops. A clock input (CP) and an output enable (OE)

are provided per 8-bit section.

The 74AVC16374 is designed to have an extremely fast propagation delay and a

minimum amount of power consumption.

To ensure the high-impedance output state during power-up or power-down, nOE should

be tied to VCC through a pull-up resistor (Live Insertion).

A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line

drive during transient (see Figure 5 and Figure 6).

2. Features and benefits

? Wide supply voltage range from 1.2 V to 3.6 V

? Complies with JEDEC standards:

? JESD8-7 (1.2 V to 1.95 V)

? JESD8-5 (1.8 V to 2.7 V)

? JESD8-1A (2.7 V to 3.6 V)

? CMOS low power consumption

? Input/output tolerant up to 3.6 V

? Dynamic Controlled Output (DCO) circuit dynamically changes output impedance,

resulting in noise reduction without speed degradation

? Low inductance multiple VCC and GND pins to minimize noise and ground bounce

? Supports Live Insertion