1. General description

The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state

output is controlled by the output enable input (nOE). A HIGH level at pin nOE causes the output to

assume a high-impedance OFF-state.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times

across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range

from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry

disables the output, preventing the damaging backflow current through the device when it is

powered down.

This device has the input-disable feature, which allows floating input signals. The inputs are

disabled when the output enable input nOE is HIGH.

2. Features and benefits

? Wide supply voltage range from 0.8 V to 3.6 V

? High noise immunity

? Complies with JEDEC standards:

? JESD8-12 (0.8 V to 1.3 V)

? JESD8-11 (0.9 V to 1.65 V)

? JESD8-7 (1.2 V to 1.95 V)

? JESD8-5 (1.8 V to 2.7 V)

? JESD8-B (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F Class 3A exceeds 5000 V

? MM JESD22-A115-A exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Low static power consumption; ICC = 0.9 μA (maximum)

? Latch-up performance exceeds 100 mA per JESD78 Class II

? Inputs accept voltages up to 3.6 V

? Low-noise overshoot and undershoot < 10 of VCC

? Input-disable feature allows floating input conditions

? IOFF circuitry provides partial Power-down mode operation

? Multiple package options

? Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP2G240GT屬于集成電路（IC） > 緩沖器，驅(qū)動器，接收器，收發(fā)器。安世半導體(中國)有限公司制造生產(chǎn)的74AUP2G240GT緩沖器，驅(qū)動器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動器、接收器和收發(fā)器允許隔離對某個電路的邏輯信號的訪問，以用于另一電路。緩沖器將其輸入信號（不變或反相）傳遞到其輸出，并可能用于清除弱信號或驅(qū)動負載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進行隔離通信。