74AUP2G157DC集成電路（IC）的信號(hào)開(kāi)關(guān)多路復(fù)用器解碼器規(guī)格書(shū)PDF中文資料

1. General description

The 74AUP2G157 is a single 2-input multiplexer which select data from two data inputs (I0 and I1)

under control of a common data select input (S). The state of the common data select input

determines the particular register from which the data comes. The output (Y, Y) presents the

selected data in the true (non-inverted) and complement form. The enable input (E) is active LOW.

When E is HIGH, the output Y is forced LOW and the output Y is forced HIGH regardless of all

other input conditions.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times

across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic

power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry

disables the output, preventing the damaging backflow current through the device when it is

powered down.

2. Features and benefits

? Wide supply voltage range from 0.8 V to 3.6 V

? High noise immunity

? Complies with JEDEC standards:

? JESD8-12 (0.8 V to 1.3 V)

? JESD8-11 (0.9 V to 1.65 V)

? JESD8-7 (1.2 V to 1.95 V)

? JESD8-5 (1.8 V to 2.7 V)

? JESD8-B (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F Class 3A exceeds 5000 V

? MM JESD22-A115-A exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Low static power consumption; ICC = 0.9 μA (maximum)

? Latch-up performance exceeds 100 mA per JESD 78 Class II

? Inputs accept voltages up to 3.6 V

? Low noise overshoot and undershoot < 10 of VCC

? IOFF circuitry provides partial Power-down mode operation

? Multiple package options

? Specified from -40 °C to +85 °C and -40 °C to +125 °C