1. General description

The 74AUP1G57 is a configurable multiple function gate with Schmitt-trigger inputs. The device

can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter

and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. This device

ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to

3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

? Wide supply voltage range from 0.8 V to 3.6 V

? CMOS low power dissipation

? High noise immunity

? Overvoltage tolerant inputs to 3.6 V

? Low noise overshoot and undershoot < 10 of VCC

? IOFF circuitry provides partial power-down mode operation

? Latch-up performance exceeds 100 mA per JESD 78 Class II

? Low static power consumption; ICC = 0.9 μA (maximum)

? Complies with JEDEC standards:

? JESD8-12 (0.8 V to 1.3 V)

? JESD8-11 (0.9 V to 1.65 V)

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8C (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F exceeds 5000 V

? MM JESD22-A115-A exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Multiple package options

? Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP1G57GW屬于集成電路（IC） > 門和反相器 - 多功能，可配置。安世半導(dǎo)體(中國(guó))有限公司制造生產(chǎn)的74AUP1G57GW門和反相器 - 多功能，可配置可配置邏輯柵極系列產(chǎn)品能以與標(biāo)準(zhǔn)邏輯柵極類似的方式，對(duì)單個(gè)邏輯信號(hào)執(zhí)行基本邏輯運(yùn)算，但并非局限于一個(gè)特定功能（例如 AND、NAND 等）。它們通常在內(nèi)部使用少量邏輯門來(lái)實(shí)現(xiàn)，經(jīng)過(guò)選擇和互連后，以便通過(guò)選擇操作數(shù)據(jù)所應(yīng)用的輸入以及任何未使用的輸入在驅(qū)動(dòng)后的邏輯狀態(tài)，來(lái)配置所實(shí)現(xiàn)的整體邏輯功能。