1. General description

The 74ALVT16823 is an 18-bit positive-edge triggered D-type flip-flop with 3-state outputs, reset

and enable.

The device can be used as two 9-bit flip-flops or one 18-bit flip-flop. The device features clock

(nCP), clock enable (nCE), master reset (nMR) and output enable (nOE, inputs each controlling

9-bits. When nCE is LOW, the flip-flops will store the state of their individual D-inputs that meet the

set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE

causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not

affect the state of the flip-flops. A LOW on nMR will reset the flip-flops LOW. Bus hold data inputs

eliminate the need for external pull-up resistors to define unused inputs

2. Features and benefits

? Wide supply voltage range from 2.3 V to 3.6 V

? Overvoltage tolerant inputs to 5.5 V

? BiCMOS high speed and output drive

? Direct interface with TTL levels

? Bus hold on data inputs

? Power-up 3-state

? IOFF circuitry provides partial Power-down mode operation

? Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops

? Ideal where high speed, light loading, or increased fan-in are required with MOS

microprocessors

? Live insertion and extraction permitted

? Power-up reset

? No bus current loading when output is tied to 5 V bus

? Output capability: +64 mA to -32 mA

? Latch-up performance exceeds 500 mA per JESD 78 Class II Level B

? ESD protection:

? MIL STD 883, method 3015: exceeds 2000 V

? MM: exceeds 200 V

? Specified from -40 °C to 85 °C

74ALVT16823DGG屬于集成電路（IC） > 觸發(fā)器。安世半導(dǎo)體(中國)有限公司制造生產(chǎn)的74ALVT16823DGG觸發(fā)器觸發(fā)器是能夠存儲單個邏輯狀態(tài)或信息“位”的基本數(shù)字存儲器件。這些器件至少有兩個輸入；一個或多個用于傳遞要存儲的數(shù)據(jù)，另一個用于指示存儲該數(shù)據(jù)的時間點。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對提供給其輸入的信號有不同的響應(yīng)，可用于實現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時鐘信號時才會改變。