1 General description

The 74ALVT16821 high-performance BiCMOS device combines low static and dynamic

power dissipation with high speed and high output drive. It is designed for VCC operation

at 2.5 V or 3.3 V with I/O compatibility to 5 V.

The 74ALVT16821 has two 10-bit, edge triggered registers, with each register coupled to

a 3-state output buffer. The two sections of each register are controlled independently by

the clock (nCP) and output enable (nOE) control gates.

Each register is fully edge triggered. The state of each D input, one set-up time before

the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flops Q output.

The 3-state output buffers are designed to drive heavily loaded 3-state buses,

MOS memories, or MOS microprocessors.

The active low output enable (nOE) controls all ten 3-state buffers independent of the

register operation. When nOE is LOW, the data in the register appears at the outputs.

When nOE is HIGH, the outputs are in high-impedance OFF-state, which means they will

neither drive nor load the bus.

2 Features and benefits

? 20-bit positive-edge triggered register

? 5 V I/O compatible

? Multiple VCC and GND pins minimize switching noise

? Bus hold data inputs eliminate the need for external pull-up resistors to hold unused

inputs

? Live insertion and extraction permitted

? Power-up reset

? Power-up 3-state

? Output capability: +64 mA and -32 mA

? Latch-up protection:

– JESD78: exceeds 500 mA

? ESD protection:

– MIL STD 883, method 3015: exceeds 2000 V

– MM: exceeds 200 V

74ALVT16821DGG屬于集成電路（IC） > 觸發(fā)器。安世半導(dǎo)體(中國)有限公司制造生產(chǎn)的74ALVT16821DGG觸發(fā)器觸發(fā)器是能夠存儲單個邏輯狀態(tài)或信息“位”的基本數(shù)字存儲器件。這些器件至少有兩個輸入；一個或多個用于傳遞要存儲的數(shù)據(jù)，另一個用于指示存儲該數(shù)據(jù)的時間點。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對提供給其輸入的信號有不同的響應(yīng)，可用于實現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時鐘信號時才會改變。