1 General description

The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting

registered transceiver. Two 8-bit back to back registers store data flowing in both

directions between two bidirectional buses. Data applied to the inputs is entered and

stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock

enable (nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but

is only accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow

from A inputs to B outputs is the same as for B inputs to A outputs.

2 Features and benefits

? CMOS low-power consumption

? Multibyte flow-through pinout architecture

? Low inductance, multiple center power and ground pins for minimum noise and ground

bounce

? Direct interface with TTL levels

? Output drive capability 50 Ω transmission lines at 85 °C

? Complies with JEDEC standard JESD8-B

74ALVCH16952DGG屬于集成電路（IC） > 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器。安世半導(dǎo)體(中國)有限公司制造生產(chǎn)的74ALVCH16952DGG緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動(dòng)器、接收器和收發(fā)器允許隔離對(duì)某個(gè)電路的邏輯信號(hào)的訪問，以用于另一電路。緩沖器將其輸入信號(hào)（不變或反相）傳遞到其輸出，并可能用于清除弱信號(hào)或驅(qū)動(dòng)負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進(jìn)行隔離通信。