1 General description

The 74ALVCH162244 is a 16-bit non-inverting buffer/line driver with 3-state outputs.

The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer.

The 3-state outputs are controlled by the output enable inputs 1OE, 2OE, 3OE and

4OE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state.

The 74ALVCH162244 is designed with 30 Ω series resistors in both HIGH and LOW

output states.

The 74ALVCH162244 has active bus hold circuitry which is provided to hold unused or

floating data inputs at a valid logic level. This feature eliminates the need for external

pull-up or pull-down resistors.

2 Features and benefits

? Wide supply voltage range from 1.2 V to 3.6 V

? CMOS low power consumption

? MultiByte flow-through standard pin-out architecture

? Low inductance multiple VCC and GND pins for minimum noise and ground bounce

? Direct interface with TTL levels (2.7 V to 3.6 V)

? Bus hold on all data inputs

? Integrated 30 Ω termination resistor

? Complies with JEDEC standards:

– JESD8-5 (2.3 V to 2.7 V)

– JESD8B/JESD36 (2.7 V to 3.6 V)

? ESD protection:

– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

– CDM JESD22-C101E exceeds 1000 V

74ALVCH162244DGG屬于集成電路（IC） > 緩沖器，驅動器，接收器，收發(fā)器。安世半導體(中國)有限公司制造生產(chǎn)的74ALVCH162244DGG緩沖器，驅動器，接收器，收發(fā)器邏輯緩沖器、驅動器、接收器和收發(fā)器允許隔離對某個電路的邏輯信號的訪問，以用于另一電路。緩沖器將其輸入信號（不變或反相）傳遞到其輸出，并可能用于清除弱信號或驅動負載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進行隔離通信。