74ALVC573PW集成電路（IC）的鎖存器規(guī)格書PDF中文資料

廠商型號	74ALVC573PW
參數(shù)屬性	74ALVC573PW 封裝/外殼為20-TSSOP（0.173"，4.40mm 寬）；包裝為卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶；類別為集成電路（IC）的鎖存器；產品描述：IC OCTAL D TRANSP LATCH 20TSSOP
功能描述	Octal D-type transparent latch; 3-state
封裝外殼	20-TSSOP（0.173"，4.40mm 寬）
文件大小	268.43 Kbytes
頁面數(shù)量	16 頁
生產廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-2-11 22:30:00

1. General description

The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch

and 3-state true outputs for bus-oriented applications. A latch enable (LE) input and an outputs

enable (OE) input are common to all latches.

When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this condition,

the latches are transparent, that is, a latch output will change each time its corresponding D-input

changes. When pin LE is LOW, the latches store the information that was present at the D-inputs

one set-up time preceding the HIGH-to-LOW transition of pin LE.

When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins Q0 to

Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input pin

OE does not affect the state of the latches.

The 74ALVC573 is functionally identical to the 74ALVC373, but has a different pin arrangement.

2. Features and benefits

? Wide supply voltage range from 1.65 V to 3.6 V

? 3.6 V tolerant inputs/outputs

? CMOS low power consumption

? Direct interface with TTL levels (2.7 V to 3.6 V)

? Power-down mode

? Latch-up performance exceeds 250 mA

? Complies with JEDEC standards:

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8B (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114E exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V