74ALS174D中文資料飛利浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書
74ALS174D規(guī)格書詳情
DESCRIPTION
The 74ALS174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output.
All Q outputs will be forced Low independent of clock or data inputs by a Low voltage level on the MR input. The device is useful for applications where true outputs only are required, and the clock and master reset are common to all storage elements.
FEATURES
? Four edge-triggered D flip-flops
? Buffered common clock
? Buffered asynchronous master reset
產(chǎn)品屬性
- 型號(hào)：
74ALS174D
- 制造商：
PHILIPS
- 制造商全稱：
NXP Semiconductors
- 功能描述：
Hex D flip-flop
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
TI/德州儀器 |
23+ |
NA/ |
4750 |
原裝現(xiàn)貨,當(dāng)天可交貨,原型號(hào)開票 |
詢價(jià) | ||
NS |
23+ |
DIP-16 |
20000 |
全新原裝假一賠十 |
詢價(jià) | ||
FAIRCHILD/仙童 |
2023+ |
8700 |
原裝現(xiàn)貨 |
詢價(jià) | |||
NAT |
1993 |
720 |
原裝正品現(xiàn)貨庫(kù)存價(jià)優(yōu) |
詢價(jià) | |||
FAIRCHILD/仙童 |
24+ |
SOP5.2 |
213 |
大批量供應(yīng)優(yōu)勢(shì)庫(kù)存熱賣 |
詢價(jià) | ||
TI |
23+ |
sop |
3200 |
全新原裝、誠(chéng)信經(jīng)營(yíng)、公司現(xiàn)貨銷售 |
詢價(jià) | ||
SIGN |
23+ |
NA |
9856 |
原裝正品,假一罰百! |
詢價(jià) | ||
TI/德州儀器 |
22+ |
SOP3.9 |
8000 |
原裝正品支持實(shí)單 |
詢價(jià) | ||
TI |
SOP5.2 |
650 |
正品原裝--自家現(xiàn)貨-實(shí)單可談 |
詢價(jià) | |||
PHILIPS |
新 |
48 |
全新原裝 貨期兩周 |
詢價(jià) |
