1. General description

The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with

Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data

inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary

outputs (Q and Q).

The set and reset are asynchronous active LOW inputs that operate independent of the clock

input. Information on the data input is transferred to the Q output on the LOW to HIGH transition

of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock

transition for predictable operation.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall

times.

2. Features and benefits

? Balanced propagation delays

? All inputs have Schmitt-trigger actions

? Inputs accept voltages higher than VCC

? Input levels:

? For 74AHC74: CMOS level

? For 74AHCT74: TTL level

? ESD protection:

? HBM EIA/JESD22-A114E exceeds 2000 V

? MM EIA/JESD22-A115-A exceeds 200 V

? CDM EIA/JESD22-C101C exceeds 1000 V

? Multiple package options

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C

74AHC74PW屬于集成電路（IC） > 觸發(fā)器。安世半導(dǎo)體(中國(guó))有限公司制造生產(chǎn)的74AHC74PW觸發(fā)器觸發(fā)器是能夠存儲(chǔ)單個(gè)邏輯狀態(tài)或信息“位”的基本數(shù)字存儲(chǔ)器件。這些器件至少有兩個(gè)輸入；一個(gè)或多個(gè)用于傳遞要存儲(chǔ)的數(shù)據(jù)，另一個(gè)用于指示存儲(chǔ)該數(shù)據(jù)的時(shí)間點(diǎn)。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對(duì)提供給其輸入的信號(hào)有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時(shí)鐘信號(hào)時(shí)才會(huì)改變。